1. Field of the Invention
The present invention relates generally to systems and methods for electronic signaling, and, more particularly, the present invention is directed to a multi-bit differential signaling alternative to traditional differential signaling methodologies.
2. Description of the Background
Electrical communication links have long embraced the use of differential signaling for low noise and high bandwidth data transmission. For example, high performance data channels are of increasing importance for applications such as chip-to-chip PCB (PC Board) interconnect and disk drive data channels as smaller features and lower voltages drive the economics of CMOS design away from traditional bit-per-wire I/O. Although the reasons behind using certain signaling schemes may differ for various applications, all of these (and other) communications activities reflect a need to produce continually higher bandwidth, higher speed applications, without losing the benefits of existing technologies.
Taking chip-to-chip signaling as an example, there are two important trends in CMOS digital and mixed-signal technology that are motivating designers to seek higher bandwidth off-chip signaling solutions. The first is a technology trend driven by the traditional gap between on-chip and off-chip signal bandwidth. This gap continues to widen as CMOS technology advances faster than PCB fabrication and materials technology and has become a substantial bottleneck in overall system performance.
The second trend is based on changes in the economics of chip production for high-speed and low power devices in deep sub-micron technologies. When measuring overall power consumption, silicon real estate and chip packaging costs for these devices, it is cheaper to organize the off-chip signaling into a small number of high speed serial I/O lines rather than the traditional bit-per-pin I/O organizations.
Consistent with these trends, the semiconductor industry association has projected chip-to-chip I/O links capable of 10 Gbps over 40 cm of FR-4 PCB material in near-term generations of microprocessors. For the present, commercial signaling standards have emerged in the 200 to 800 Mbps/pin range. Examples of these new high-speed signaling standards include: Hypertransport, a bus standard at 400 Mbps/pin; QRSL, a high density memory interconnect from RAMBUS that achieves 800 Mbps/pin using 4-level logic; and two LVDS standards, TIA/EIA-644-A at 655 Mbps and IEEE 1563 at 500 Mbps. At gigabit rates, Hypertransport 2 has emerged recently with a 1 Gbps/pin speed grade option at the high end. It is clear that significant opportunity exists for chip-to-chip, backplane, optical and other signaling standards with 1 to 2.5 Gbps/channel capabilities with longer term prospects for operation at 10 Gpbs.
In all of the current and proposed standards for high speed chip-to-chip links, channel coding is based on some form of differential signaling. Specifically, in a differentially encoded data bus, each bit is encoded based on an oppositely charged pair of conductors. Each state, ‘0’ or ‘1’, is encoded as one of two code words represented by the two polarities, on-off {10} or off-on {01}. Thus, the number of physical wires in the link is equal to twice the bit-width of the link.
Accordingly, differentially encoded busses have a significant disadvantage in high-speed communication links. The disadvantage of differential signaling stems from its low code density—using only half of the signaling capacity of the available transmission lines.
Although described as such, this problem with differential signaling is not limited to proposed chip-to-chip link standards within multi-chip-modules and printed circuit boards. Longer length data channels, (on the order of up to a meter in length) such as module-to-module level (backplane), and cabinet-to-cabinet communications links, are typically based on differential signaling and are characterized by similar concerns. Likewise, optical fiber based solutions for the same distance ranges typically use differential driver and receiver circuits while discarding and regenerating one of the two states at each end of a single-ended fiber channel. The overall cost and performance of all of these links can be improved using the techniques of the present invention.
Other technology trends suggest the near term adoption of differentially encoded buses in intra-chip links. (distance scales of a few centimeters, spanning the area of very large scale semiconductor devices). As lower supply voltage drives down transistor thresholds, leakage current increases significantly in the repeating buffers required. Simultaneously, higher bandwidth and smaller feature size has decreased the distance between these buffers, increasing their number and thus the total power lost to leakage current. In this environment, current-mode, differentially encoded buses are becoming popular
The present invention, in at least one preferred embodiment, provides an alternative to these differential transmission schemes using a multi-bit differential signaling methodology. The present systems and methods preferably retain the noise and loss advantages of conventional differential signaling but significantly increase the code density and use less power and fewer communication channels than comparable prior art systems.